Yong Chen Senior Research Associate Department of Computer Science Illinois Institute of Technology	Stuart Building, Room 013B 10 W. 31st Street, Chicago, IL 60616 Email: yong.chen [at] iit [dot] edu, Tel.: 312-567-3993
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Research Interests:

My research focuses on parallel and distributed computing, high-performance computing, computer architecture and systems software support for computational science in general. Specifically, my research interests include: (1) Optimizing data-access performance with effective caching, prefetching, scheduling and parallel I/O solutions (e.g. parallel file system, MPI middleware, etc.); (2) Modeling and evaluating parallel systems and applications, including profiling, benchmarking, tuning, etc.; (3) Exploiting novel programming paradigms and systems software support for computational science.

Current Projects:

• Application-Specific Optimization via Server Push I/O Architecture
  As modern multicore architectures put ever more pressure on the sluggish memory systems, computer applications become more and more data intensive. Advanced memory hierarchies and parallel file systems have been developed in recent years. However, they only provide performance for well-formed data streams, and fail to meet a more general demand. I/O has become a crucial performance bottleneck of high-end computing (HEC), especially for data intensive applications. New mechanisms and new I/O architectures need to be developed to solve the ‘I/O-wall’ problem. We propose a new I/O architecture for HEC. Unlike traditional I/O designs where data is stored and retrieved upon request, our architecture is based on an application-specific ‘Server-Push’ approach in which a data access server automatically tailors the I/O system to optimize data retrieval and data layout for best performance. Here, push means that the data access server takes decisions for in time data retrieval and smart data layout. While in time is defined as moving data from its source to destination within a window of time before it is required, smart means to layout data based on application I/O patterns, thereby fully utilizing parallel I/O and parallel file systems. The basic idea of ‘Server-Push’ is trading computing power for accurate I/O prefetching and for optimized data layout and organization. Designing the ‘Server-Push’ system includes rethinking the design at each level of memory hierarchy, from compiler to file system, to runtime system, as well as rigorous performance modeling and implementation verification. The objective of this research is three fold: 1) increasing the fundamental understanding of I/O behavior at both computing client level and file system server level; 2) providing application-specific performance optimizations using caching, prefetching, and layout optimizations based on the understanding of I/O behavior; 3) producing an effective I/O architecture that minimizes I/O access delay. We plan to increase the fundamental understanding of I/O behavior through the study of I/O access pattern identification, prefetching algorithms, data replacement strategy, data distribution strategy and extensive experimental testing. We verify the performance improvement of server-push design for various critical I/O intensive applications by using a combination of simulation and actual implementation in the PVFS2 file system. This is a joint project with Argonne National Laboratory and University of Illinois at Urbana-Champaign.
  Related publications:
  • X.-H. Sun, Y. Chen and Y. Yin, "Data Layout Optimization for Petascale File Systems", accepted to appear in Proc. of The 4th Petascale Data Storage Workshop (in conjunction with ACM/IEEE SC'09), 2009.
  • Y. Chen, S. Byna, X.-H. Sun, R. Thakur, W. Gropp. "Hiding I/O Latency with Pre-execution Prefetching for Parallel Applications", in Proc. of the ACM/IEEE SuperComputing Conference (SC'08), Austin, Texas, USA, Nov. 2008. (Best Paper finalist, Best Student Paper finalist) (acceptance rate: 59/277=21.3%)
  • S. Byna, Y. Chen, X.-H. Sun, R. Thakur, W. Gropp. "Parallel I/O Prefetching Using MPI File Caching and I/O Signatures", in Proc. of the ACM/IEEE SuperComputing Conference (SC'08), Austin, Texas, USA, Nov. 2008. (acceptance rate: 59/277=21.3%)
  • Y. Chen, S. Byna, X.-H. Sun, R. Thakur, W. Gropp. "Exploring Parallel I/O Concurrency with Speculative Prefetching", in Proc. of the 37th International Conference on Parallel Processing (ICPP'08), Portland, Oregon, USA, 2008. (acceptance rate: 81/263=30.8%)
  • S. Byna, Y. Chen and X.-H. Sun. A Taxonomy of Data Prefetching Mechanisms, in Proc. of International Symposium on Parallel Architectures, Algorithms, and Networks (ISPAN'08), 2008.
  • X.-H. Sun, S. Byna and Y. Chen. "Server-based Data Push Architecture for Multi-processor Environments", Journal of Computer Science and Technology (JCST), Vol. 22, No. 5, 641 – 652, 2007.
  • X.-H. Sun, S. Byna, and Y. Chen. Improving Data Access Performance with Server Push Architecture, in Proc. of the NSF Next Generation Software Program Workshop (in conjunction with IPDPS '07), March 2007.
  
  
• Multicore Scheduling and Data Access
  Multicore microprocessor has totally changed the landscape of what we know as (single machine) computing. It brings parallel processing into a single processor at task level. On one hand, it significantly further enlarges the performance gap between data processing and data access. On the other hand, it calls for a rethinking of system design to utilize the potential of multicore architecture. We believe the key of utilizing multicore microprocessors is to reduce data access delay. We rethink the system scheduling and support from the viewpoint of data access under multicore environments. To this end, in this research we focus on design and development of multicore specific system supports and mechanisms to reduce data access delay. Our approach is three fold: special hardware for swift data access, core-aware and context-aware scheduling and prefetching, and integrated I/O handling for data intensive application. In this project, we propose to enhance memory access performance of modern micro-architecture with specialized data prefetching and access scheduling techniques. Data prefetching, which decouples and overlaps data transfer and computation, is widely considered as an effective memory latency hiding technique. Cache misses are a common cause of CPU stalls. Using cache memories effectively enables bridging the performance gap between the processor and memory. To achieve this goal, data prefetching predicts future data accesses of a processor, initiates data fetch early on and brings the data closer to the processor before the processor requests for it. Access scheduling is an effective solution in tackling the memory performance bottleneck too. Memory access scheduling can effectively reorganize data accesses, and thus reduce the average memory access latency and improve memory bandwidth utilization. We have introduced the data access history cache architecture to support dynamic hardware prefetching and smart data management, and developed the core-aware memory access scheduling for multicore systems recently.
  Related publications:
  • X.-H. Sun and Y. Chen. "Reevaluating Amdahl's Law in the Multicore Era," (JPDC online version) to appear in Journal of Parallel and Distributed Computing, 2009.
  • S. Byna, Y. Chen, and X.-H. Sun. "Taxonomy of data prefetching for multicore processors", Journal of Computer Science and Technology, vol. 24, no. 3, pp. 405-417, May 2009.
  • Z. Fang, X.-H. Sun, Y. Chen and S. Byna. "Core-Aware Memory Access Scheduling Schemes ", in Proc. of IEEE International Parallel & Distributed Processing Symposium (IPDPS’09) (acceptance rate: 100/440=22.7%).
  • X.-H. Sun, Y. Chen and S. Byna. "Scalable Computing in Multicore Era", in Proc. of International Symposium on Parallel Algorithms, Architectures and Programming (PAAP'08), 2008.
  • Y. Chen, S. Byna, and X.-H. Sun. Data Access History Cache and Associated Data Prefetching Mechanisms, in Proc. of the ACM/IEEE Supercomputing Conference (SC'07), Reno, Nevada, USA, Nov. 2007. (acceptance rate: 54/268=20.1%)
  
  

Past Projects:

• Performance Modeling and Evaluation of Parallel Systems and Applications
  Scalability is a key factor of the design of parallel systems and algorithms. However, conventional scalabilities are designed for homogeneous parallel processing. In this project, we propose a generalized scalablity model, named isospeed-efficiency model, to characterize and evaluate general (both homogeneous and heterogeneous computing systems) parallel systems and algorithms. Through theoretical analysis, we derive methodologies of scalability measurement and prediction for general parallel systems. Experimental results verify the analytical results and confirm that the generalized scalability works well in both homogeneous and heterogeneous environments. Based on the theoretical modeling and analyses, we design a Scalability Testing and Analysis System (STAS) and provide a prototype implementation. STAS provides the facility to conduct automated scalability measure and analysis. It reduces the burden for users to evaluate the performance of algorithms and systems.
  Related publications:
  • Y. Chen, X.-H. Sun and M. Wu. "Algorithm-System Scalability of Heterogeneous Computing", Journal of Parallel and Distributed Computing (JPDC), Vol. 68, No. 11, 1403 – 1412, 2008.
  • Y. Chen and X.-H. Sun. STAS: A Scalability Testing and Analysis System, in Proc. of IEEE International Conference on Cluster Computing 2006(Cluster'06), Sept. 2006. (acceptance rate: 42/127=33.1%)
  • X.-H. Sun, Y. Chen and M. Wu. Scalability of Heterogeneous Computing, in Proc. of 34th International Conference on Parallel Processing (ICPP'05). June 2005. (acceptance rate: 69/241=28.6%)
  
  
• Design Information Framework Project
  Design Information Framework (DIF) is a platform that facilitates cross-disciplinary sharing of research and development information. This project was led by Prof. Keiichi Sato of IIT Institute of Design, and please see Prof. Sato's website for more details. I parcitipated this project as a summer intern. The DIF system was primarily implemented with JDK 1.4.2 and open-source database system MySQL 4.2.
  Related publications:
  • E.-C. Jung, K. Sato, Y. Chen, X. He, T. MacTavish and D. Cracchiolo. DIF Knowledge Management System: Bridging Viewpoints for Interactive System Design, in Proc. of 11th International Conference on Human-Computer Interaction (HCI'05). Las Vegas, July 2005.
  
  
• Research and Development of Integrated User Environment Tools for Supercomputers
  This project was led by Prof. Guoliang Chen at National High-Performance Computing Center (at HeFei) in University of Science and Technology of China. I participated the development of a remote parallel debugger for large-scale supercomputers. The debugger leverages the functionality of two serial debuggers, gdb and dbx, and integrates parallel debugging features. The debugger was developed with C, Java & CORBA (for user interface and the communication between remote users and supercomputers). In addition, I studied and compared two dominant parallel programming models, Single Memory Model (such as MPI) and Hybrid Memory Model (such as MPI+OpenMP), proposed effective way of utilizing these two models, and verified the proposal with experimental testing on Dawning3000 supercomputer, one of the leading supercomputers in China at that time.
  Related publications:
  • Y. Chen, G. Chen, C. Li and J. He. "Hybrid Programming Model Research on SMP Cluster Architecture". Mini-Micro Systems, Vol.25, No.10 P.1763-1767. 2004. (In Chinese)
  • Y. Chen, C. Li, H. An, Q. Zheng and Z. Chen. "Remote Parallel Debugger Based on Dawning3000 Parallel Machine". Journal of Computer Science, Vol.31, No.3, P.179-182. 2004. (In Chinese)
  • Y. Chen, K. He, Z. Lu and C. Yan. "Design and Implementation of A Parallel Debugger for Cluster System". Journal of Computer Engineering, Vol.30, No.9, P.50-52. 2004. (In Chinese)
  • Y. Chen, G. Chen, Y. Xu and J. Shan. Implementation and Evaluation of MPI+OpenMP Programming Model on Dawning3000, in Proc. of the 21st IASTED International Conference, Applied Informatics. Innsbruck, Austria. 2003. 732-737.
  
  

Invited Talks:

• The Server-Push Architecture for High-End Computing, NSF HECURA-FSIO Conference, poster session, Aug. 10th, 2009, National Science Foundation, Arlington, Virginia.
• A Hybrid Data Prefetching Architecture for Data Access Efficiency, ACM/IEEE Supercomputing Conference (SC’08), Doctoral Showcase, Nov. 20th, 2008, Austin, Texas.
• Hiding I/O Latency with Pre-execution Prefetching for Parallel Applications, ACM/IEEE Supercomputing Conference (SC’08), Nov. 20th, 2008, Austin, Texas.
• Exploring Parallel I/O Concurrency with Speculative Prefetching. The 37th International Conference on Parallel Processing (ICPP’08), Sept. 10th, 2008, Portland, Oregon.
• Server-Push Architecture for Improving I/O Access Performance. NSF Collaborative Expedition Workshop, Jun. 10th, 2008, National Science Foundation, Arlington, Virginia.
• Data Access History Cache and Associated Data Prefetching Mechanisms. ACM/IEEE Supercomputing Conference (SC’07), Nov. 13th, 2007, Reno, Nevada.
• The Server-Push I/O Architecture for High-End Computing. ACM/IEEE Supercomputing Conference (SC’07), poster session, Nov. 13th, 2007, Reno, Nevada.
• Implementation and Evaluation of MPI+OpenMP Programming Model on Dawning3000. The 21st IASTED International Multi-Conference on Applied Informatics (AI’03), Feb. 12th, 2003, Innsbruck, Austria.