Dr. Pen-Chung Yew

William Norris Land-Grant Chair Professor and Head
Department of Computer Science & Engineering
University of Minnesota at Twin Cities

Time : Monday, September 9th, 11:00 am  

Location: SB 238

 

Multithreading: A Cost-Effective Way to Enhance Performance for Future Generations of Microprocessors and Their Applications

Abstract

The performance of microprocessors has grown dramatically in the last 20 years. However, superscalar architectures seem to be approaching their limits in extending that growth. Multithreading has recently been recognized as a promising way to extend processor architectures beyond exploring only instruction-level parallelism (ILP). Unlike machine instructions in ILP, "threads" are a rather abstract object. The composition of a thread can be as small as a few basic blocks or it can be extended to several iterations of a loop, or even an entire procedure. Exploring both thread-level parallelism (TLP) and ILP allows us to merge two distinct architecture families, namely, microprocessors and multiprocessors, and thereby leverage their strength to create a new breed of processor architectures. In this talk, we will discuss important architectural issues in the multithreaded architectures and their compilation techniques.

 

Short Bio of the Speaker

Pen-Chung Yew received his PhD in computer science from the University of Illinois at Urbana-Champaign.

He is the William Norris Land-Grant Chair Professor and the Head of the Department of Computer Science and Engineering, University of Minnesota. Previously, he was an Associate Director of the Center for Supercomputing Research and Development at the University of Illinois at Urbana-Champaign. From 1991 to 1992, he served as the Program Director of the Microelectronic Systems Architecture Program in the Division of Microelectronic Information Processing Systems at the National Science Foundation, Washington, D.C.

Pen-Chung Yew is an IEEE Fellow. He is currently the Editor-in-Chief of the IEEE Trans. on Parallel and Distributed Systems. He has served on the program committee of various conferences. He also served as a co-chair of the 1990 International Conference on Parallel Processing, a general co-chair of the 1994 International Symposium on Computer Architecture, the program chair of the 1996 International Conference on Supercomputing, and a program co-chair of the 2002 International Conference on High Performance Computer Architecture. He has also served on the editorial boards of the IEEE Transactions on Parallel and Distributed Systems from 1992 to 1996, and Journal of Parallel and Distributed Computing from 1989 to 1995.

His research interests include high-performance multiprocessor system design, parallelizing compilers, computer architecture, runtime dynamic compilation, and performance evaluation..

 

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